(1) Field of the Invention
This invention relates to a method for cleaning a semiconductor substrate, and more specifically to a method for cleaning polishing slurry particles and metallic residues from the surface of a semiconductor substrate after chemical-mechanical polishing.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits CMP (Chemical-Mechanical Polishing) can be used to produce smooth topographies on surfaces deposited on the semiconductor substrates. Rough topography results when metal conductor lines are formed over a substrate containing device circuitry. The metal conductor lines serve to interconnect discrete devices, and thus form integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin layers of insulating material and holes formed through the insulating layers provide electrical access between successive conductive interconnection layers. In such wiring processes, it is desirable that the insulating layers have smooth surface topography, because it is difficult to lithographically image and pattern layers applied to rough surfaces. CMP can, also, be used to remove different layers of material from the surface of a semiconductor substrate. For example, following contact hole formation in an insulating layer, a metallization layer is blanket deposited and then CMP is used to produce planar metal contact studs embedded in the insulating material layer.
Briefly, the CMP processes involve holding and rotating a thin, flat substrate of the semiconductor material against a wetted polishing surface under controlled chemical, pressure and temperature conditions. A chemical slurry containing a polishing agent, such as alumina or silica, is used as the abrasive material. Additionally, the chemical slurry contains selected chemicals which etch various surfaces of the substrate during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface.
CMP of dielectric layers, such as silicon oxide, is widely accepted as the choice of planarization process for integrated circuit technologies having dense topographical features in multilevel metal interconnection structures. Additionally, CMP of blanket deposited tungsten layers is widely used for the formation of high-aspect-ratio interlevel connecting plugs.
An important challenge in CMP is to produce a clean substrate surface following polishing. Therefore, a primary concern with the use of CMP is the efficient and complete removal of the polishing slurry and other polishing residues and particulates following polishing in order to prevent introduction of defects into the polished product. Ideally, post-CMP cleaning should remove all polishing slurry, polishing residues and particulates in a quick and repeatable fashion without introducing additional defects or damage to the substrate surface. State-of-the art cleaning procedures following CMP typically use a water rinse and a scrub with a soft rotating brush to remove slurry residue from the surface of the semiconductor substrate. However, brush scrubbing can introduce scratches onto the substrate surface and is, also, a source of cross-contamination between sequentially processed substrates.
Post-CMP substrate cleaning is a subject of concern in current CMP technology, as shown in numerous patents. U.S. Pat. No. 5,704,987 entitled "Process For Removing Residue From A Semiconductor Wafer After Chemical-Mechanical Polishing" granted Jan. 6, 1998 to Cuc Kim Huynh et al describes a method for removing residual slurry particles from a semiconductor substrate surface following CMP (Chemical-Mechanical Planarization). The cleaning method uses a polishing pad and a surfactant, such as TMAH (tetramethylammonium hydroxide), in a first step followed by a second cleaning step which uses a polishing pad with water.
U.S. Pat. No. 5,078,801 entitled "Post-Polish Cleaning Of Oxidized Substrates By Reverse Colloidation" granted Jan. 7, 1992 to Farid A. Malik shows a process for removing residual silica particles from a post-polished silicon substrate. The process utilizes a KOH-based solution, followed by rinsing in de-ionized water, ultrasonic agitation in de-ionized water, and then drying the silicon substrate.
U.S. Pat. No. 5,632,667 entitled "No Coat Backside Wafer Grinding Process" granted May 27, 1994 to Michael R. Earl et al describes a method for grinding the backside surface of a semiconductor substrate, in which an organic acid cooling fluid, such as citric acid, is utilized during the grinding procedure to prevent particulates and residue from the substrate during the grinding from adhering to the metal bond pads of integrated circuits formed on the front side of the semiconductor substrate. The organic acid cooling fluid has a pH between about pH=3.5 and pH=5.5.
U.S. Pat. No. 5,597,443 entitled "Method And System For Chemical Mechanical Polishing Of Semiconductor Wafer" granted Jan. 28, 1997 to Eugene O. Hempel describes a post-CMP cleaning step using a NH.sub.4 OH rinse.
U.S. Pat. No. 5,679,169 entitled "Method For Post Chemical-Mechanical Planarization Cleaning Of Semiconductor Wafers" granted Oct. 21, 1997 to David Gonzales et al shows a post-CMP cleaning method using a pre-clean step using a basic solution, followed by cleaning in an ammonia, TMAH, or citric acid rinse, and then dipping the substrate in a hydrogen fluoride solution.
The present invention is directed to a novel method of post-CMP cleaning of semiconductor substrates. The method of the present invention, which has been successfully applied to both post-oxide-CMP cleaning and post-tungsten-CMP cleaning, utilizes multi-chemical spray cleaning, requires less CMP processing time, has lower cost than conventional post-CMP cleaning methods and produces a polished surface having fewer particulate and residue defects.